A semiconductor test apparatus has heretofore been known as an apparatus which conducts a test with respect to various semiconductor devices such as a logic IC and a semiconductor memory.
Examples of the tests conducted by this semiconductor test apparatus include a function test, a direct-current characteristic test (DC parameter test), an alternating-current characteristic test (AC parameter test) and the like.
Among these tests, the function test is a test conducted for guaranteeing the function of the semiconductor device. For example, as shown in FIG. 5, a test pattern signal from a test pattern generator 11 is supplied to an IC to be tested (hereinafter referred to as a device under test “DUT”) 12, and an output signal is compared with an expected value pattern by a comparator 13 to judge whether or not various functions of the DUT 12 are satisfactory.
More specifically, the function test of the DUT 12 is performed by a semiconductor test circuit 10 constituted as shown in FIG. 6.
In the figure, test pattern data with respect to one DUT (semiconductor device) 12 having a plurality of pins is stored in a memory (expected value memory) 14 together with expected value data S to be sent to the comparator 13.
A test pattern signal applied to the DUT 12 by the test pattern generator 11 based on the test pattern data of the memory 14 is generated in synchronization with a reference clock signal CLK of a reference clock generator 15, and is supplied to an input terminal i of the DUT 12 through a DUT input delay circuit (timing generator) 16 having variable delay circuits DL1, SK1.
Moreover, a reference clock signal of the reference clock generator 15 is also supplied as a strobe signal STRB to a clock terminal of a D-type flop-flop circuit (hereinafter referred to as “DF/F”) 13-1 of the comparator 13 through a comparison timing delay circuit 17 having variable delay circuits DL2, SK2.
A delay amount Tpd is set to the variable delay circuits DL1, SK1, DL2, SK2 by a program control of a control unit 18.
Among them, the variable delay circuits DL1, DL2 are delay circuits capable of defining a time phase with respect to the DUT 12 by a user program.
On the other hand, the variable delay circuits SK1, SK2 correct the phase with respect to the DUT 12 into a predetermined value, that is, calibrate hardware, because the delay amount Tpd of the hardware including the above-described DL1, DL2 and the like fluctuates with an ambient temperature change or elapse of time.
An output (response output signal) of the DUT 12 is input into the DF/F 13-1 of the comparator 13, and an output is input into an agreement circuit (exclusive-OR circuit; Ex-OR) 13-2. Here, the output is compared with the expected value data S=“1” from the memory 14, and a comparison result is input into a DF/F 13-3.
When an output (C point) of the DF/F 13-1 is “L” (or “H”) in this comparator 13, the output disagrees (or agrees) with the expected value data S=“1”, therefore an output (E point) of the disagreement circuit 13-2 turns to “H” (or “L”), an output (F point) of the DF/F 13-3 turns to “H” (or “L”), and a result of comparison in this comparator 13 is Fail (or Pass).
By the way, when the function test of the DUT 12 is performed, test pattern signals input into a plurality of, several tens to several hundreds of pins in the DUT 12 are preferably synchronized, respectively.
However, a phase delay time, that is, a difference of timing is generated from a difference of each path in each test pattern signal.
The difference of the path, which causes generation of the phase delay time is made by a difference of a physical condition, a change of the path in a waveform shaping unit (portion for forming an output signal from the test pattern generator 11 in accordance with a circuit constitution of the DUT 12, not shown), thermal influence on a semiconductor device for use in each path and the like.
Therefore, an error is made in the comparison result in the comparator 13 by a shift of synchronization of each test pattern signal, and correct function test has not been performed.
To solve the problem, in a case where the function test is performed using the semiconductor test apparatus 10, the test pattern signals are adjusted to be synchronized for each test pattern signal at an initializing time.
In general, a frequency measurement unit or the like is used in measuring the delay amount Tpd of the test pattern signal in order to synchronize each test pattern signal.
It is to be noted that the measurement of the delay amount Tpd of the test pattern signal is not limited to the use of the frequency, and, for example, a reflected wave or the like is usable.
A method is performed as follows in which the delay amount Tpd of the test pattern signal is measured using the frequency measurement unit, and a delay amount set value of the variable delay circuit DL1 is applied in such a manner as to bring the delay amount Tpd close to the target value.
It is to be noted that a variable range of the variable delay circuit DL1 is set to τ (1 to n)=0 ns to 20 ns, and it is assumed that a first delay amount set value in the DUT input delay circuit 16 is set to an intermediate value τ1=10 ns of the variable range τ(1 to n) of the variable delay circuit DL1. It is also assumed that the target value is set to 100 nanoseconds (ns).
Moreover, transition of the delay amount set value of the variable delay circuit DL1 is shown in FIG. 7.
First, in the frequency measurement unit, the delay amount of the test pattern signal is measured by a loop frequency.
It is assumed that the delay amount measured value is 104 ns in first measurement (τ1=10 ns).
Next, the delay amount measured value (104 ns) is compared/judged with the target value (100 ns). As a result of judgment, since the delay amount measured value exceeds the target value, the delay amount set value of the variable delay circuit DL1 in the DUT input delay circuit 16 is calculated like τ2=τ1−(τ1/2^1)=5 ns.
Moreover, the delay amount Tpd of the variable delay circuit DL1 is set in such a manner as to indicate the calculated delay amount set value.
Next, it is assumed that the delay amount measured value is 99 ns in second measurement.
In this case, since the delay amount measured value is below the target value, the delay amount set value is calculated like τ3=τ2+(τ1/2^2)=7.5 ns.
Moreover, the calculated delay amount set value is set as the delay amount Tpd of the variable delay circuit DL1.
It is assumed that the delay amount measured value is 101.5 ns in third measurement.
In this case, since the delay amount measured value exceeds the target value, the delay amount set value is calculated like τ4=τ3−(τ1/2^3)=6.25 ns, and is set as the delay amount Tpd of the variable delay circuit DL1.
It is assumed that the delay amount measured value is 100.25 ns in fourth measurement.
In this case, since the delay amount measured value exceeds the target value, the delay amount set value is calculated like τ5=τ4−(τ1/2^4)=5.625 ns, and is set as the delay amount Tpd of the variable delay circuit DL1.
Subsequently, it is similarly assumed that the delay amount measured value is 99.625 ns in fifth measurement. Then, in this case, since the delay amount measured value is below the target value, the delay amount set value is calculated like τ6=τ5−(τ1/2^5)=5.9375 ns, and is set as the delay amount Tpd of the variable delay circuit DL1.
Moreover, it is assumed that the delay amount measured value is 99.9375 ns in sixth measurement. Then, also in this case, since the delay amount measured value is below the target value, the delay amount set value is calculated like τ7=τ6−(τ1/2^6)=6.09375 ns, and is set as the delay amount Tpd of the variable delay circuit DL1.
Thus, in i-th measurement, the delay amount Tpd of the variable delay circuit DL1 is decreased or increased in a binary form by τ1/2^(i−1)ns depending on whether the delay amount measured value is above or below the target value in i−1-th measurement, and the delay amount measured value is brought close to the target value.
The measuring while driving the delay amount measured value into the target value in the binary form in this manner is referred to as binary search.
According to this method, the frequency measurement unit applies the delay amount Tpd of the variable delay circuit DL1 for each path through which each test pattern signal passes in such a manner as to synchronize all input timings of the respective test pattern signals input into the plurality of pins of the DUT 12. Therefore, initial adjustment at the initializing time is possible in the function test of the DUT 12 performed using the semiconductor test apparatus 10.
However, in the variable delay circuit DL1 of the DUT input delay circuit 16, the delay amount Tpd fluctuates, for example, by a change of ambient temperature of IC or power voltage applied to the IC, manufacturing fluctuation of the IC, fluctuation of self heating amount and the like. By this fluctuation, as shown in FIG. 8, discontinuity is generated for each 1CLK frequency divider.
Moreover, in other words, the delay amount Tpd including the discontinuities is a sequence including a decrease in a part and having an ascending order. Therefore, it cannot be said that it is necessarily appropriate to search for the target value only by the binary search assuming a pure ascending-order sequence as a search target (i.e., the use of the only binary search as the method of measuring the delay amount Tpd of the test pattern signal).
In this case, it is considered that a portion which cannot be searched for by the binary search is compensated by sequential search.
A value agreeing with the target value is checked in order from an end of an array in the sequential search. Therefore, when elements of the array increase, much time is required for the searching, but the array does not have to be arrayed in an ascending or descending order.
On the other hand, in the binary search, a medium value (median) of the array is compared with a value (target value) to be searched for. In a case where the respective values are not equal to each other, a first half (or a latter half) of the array is removed, and the medium value of a remaining latter half (or first half) part is compared with the target value. The comparison of the respective values and halving of the array are repeatedly performed until the medium value agrees with the target value. Therefore, although a searching time can be shortened in the binary search, it is a condition that the array be arrayed in the ascending or descending order.
Moreover, since the delay amount Tpd of the test pattern signal in the conventional semiconductor test apparatus has a waveform (serrated waveform) of the ascending-order array including the decrease in a part, the searching range is limited as much as possible by the binary search, the target value is searched for by the sequential search in this limited searching range, and accordingly it is possible to shorten the searching time without dropping measurement precision.
That is, it is possible to realize both the reduction of the searching time by the binary search and the prevention of the drop of the measurement precision by the sequential search.
Specifically, for example, as shown in FIG. 9, when the vicinity of a middle of the delay amount Tpd having the same continuous tilt or a larger portion (e.g., A point, etc., when there is not any discontinuity within a lower half range in a searching range of the sequential search centering on a binary search result) is searched, the target value can be normally searched in the searching range by the sequential search, because any discontinuity does not exist in the searching range.
However, even when the binary search and the sequential search are used together, the target value cannot be normally searched for in some case.
For example, in a case where the binary search result is in the vicinity of the discontinuity of the delay amount Tpd (the vicinity of a valley of the serrated waveform, e.g., point B, etc. in the figure), the sequential search in an increasing direction is possible. However, when the sequential search is performed in a decreasing direction, a value larger than the target value is again searched for at a time approaching the discontinuity. Therefore, the search in the searching range ends until the target value is found, and there has been a problem that the target value cannot be normally searched for.
Especially, in a case where the target value of the test pattern signal is searched for by a combination of the binary search and the sequential search in the conventional semiconductor test apparatus, as shown in FIG. 10, a slight difference is sometimes made between a VD delay characteristic of the binary search and that of the sequential search.
This difference has been made by an influence of hysteresis of the binary search.
The influence of hysteresis mentioned herein is an influence of a previously set edge on a presently set edge, and indicates that a VD delay error appears when an influence amount changes based on a size of time difference between the previous and present edges.
It is to be noted that FIG. 10 shows the difference for ease of description. An actual difference appears at random. The difference is random because the position of the edge of the previous cycle changes every search in the binary search.
As shown in the figure, a delay amount Tpdb indicating a target value Exp agrees with B1 and B2 points in a graph showing the VD delay characteristic of the binary search. However, the delay amount Tpdb agrees only with B3 point in a graph showing the VD delay characteristic of the sequential search. Moreover, the B3 point is not included in the searching range of the sequential search centering on the B1 point.
From this, when the binary search is executed to fine the B1 point, B3 cannot be found even if the sequential search is executed, and there has been a problem that the searching cannot be normally performed.
The present invention has been developed to solve the above-described problem, and an object thereof is to provide a search circuit of a target value, in which normal and secure search for a target value Exp (delay amount Tpdb) is possible even in a sequence including a decrease of the value in a part and having an ascending order (e.g., characteristic of a delay amount Tpd with respect to a set value of a timing VD) and in which further the use of both binary search and sequential search is possible and which realizes both reduction of a searching time and prevention of drop of measurement precision, a method of searching for a target value, and a semiconductor test apparatus using this method.